1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming 3-D semiconductor devices, such as FinFET devices, using a replacement gate technique, and a novel 3-D device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If there is no voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate voltage is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called FinFET device has a three-dimensional (3-D) structure. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance, while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance capability and reliability of such devices.
For many early device technology generations, the gate structures of most transistor elements have been comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-20 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
One well-known processing method that has been used for forming a FinFET device with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. As it relates to the formation of the sacrificial and replacement gate structures, one typical replacement gate technique generally involves the following steps: 1) performing an etching process through a patterned mask layer to define a plurality of trenches in a semiconducting substrate which thereby defines a plurality of fin structures; 2) over-filling the trenches with an insulating material, such as silicon dioxide; 3) performing a chemical mechanical polishing (CMP) process using the hard mask layer as a polish-stop to remove excess amounts of the insulating material; 4) performing an etch-back etching process to remove a desired amount of the insulating material from within the trenches until such time as only the desired amount of the insulating material remains positioned in the bottom of the trenches (hereinafter referred to as the “CMP/etch-back” process); 5) forming a) a layer of material for a sacrificial gate insulation layer, b) depositing a layer of material for a sacrificial gate electrode and c) depositing a layer of material for a gate cap layer; 6) patterning the layers referenced in steps 5a-c to define a sacrificial gate structure; 7) forming a silicon nitride sidewall spacer adjacent the sacrificial gate structure; 8) depositing a layer of insulating material on the device and performing a CMP process that stops on the gate cap layer; 9) performing a plurality of etching processes to remove the gate cap layer, the sacrificial gate electrode and the sacrificial gate insulation layer to thereby define a gate cavity that is laterally defined by the inner walls of the spacers; 10) depositing a final gate insulation layer and one or more metal layers in the gate cavity; and 11) performing a CMP process to remove excess portions of the final gate insulation layer and the various metal layers to thereby define the final gate structure for the FinFET device.
The above-described replacement gate technique, while effective, is not without its problems. First, the above-described process sequence is not readily transferable to FinFET devices when there is a desire to make another FinFET device to change the fin height, e.g., to change the fin height from 5 nm to 15 or 20 nm. That is, the etching processes that are performed to pattern the sacrificial gate insulation layer, the sacrificial gate electrode layer and the gate cap layer are, more or less, based upon the final desired fin height of the fins in the device. Thus, when exploring potential changes to product designs or actually implementing a change in the fin height on a production device, the patterning process performed on previously manufactured devices may not simply be used on the new devices, i.e., a new gate patterning process sequence may need to be tested and qualified for making the newly designed product, all at great time and expense. As another example, using the above-described process flow, the fins are more susceptible to damage because the patterning of the dummy gate polysilicon material is non-selective relative to the silicon fins and may result in damage to the fins if the hard mask used during the poly etching process is compromised.
The present disclosure is directed to various methods of forming 3-D semiconductor devices, such as FinFET devices, using a replacement gate technique, and to novel 3-D devices that may solve or reduce one or more of the problems identified above.